1. Technical Field
This invention generally relates to semiconductor devices and more specifically relates to an inductor on a conductive substrate.
2. Background Art
Since its development some decades ago, the integrated circuit (IC) has been improved and enhanced numerous times. Radio frequency integrated circuits (RF ICs) represent a single manifestation of the impressive array of IC embodiments that have arisen as a result of the considerable research and development in the field. Spiral inductors are used extensively to integrate RF functions onto ICs. The typical inductor consists of a spiral arranged in a layer of metal near the top of the wafer, a drop-down via connecting the spiral to the next metal level, and an underpass providing a connecting point exterior to the spiral structure.
Although the spiral inductor arrangement works well on chips with semi-insulating substrates like gallium arsenide (GaAs), it becomes problematic when it is used with semiconducting substrates like silicon (Si). The reason for this arises from the fact that electric fields cause current to flow in nearby conductive media. This induced current in turn causes a power loss characterized by the relationship P=I2R where I is the current and R is the resistivity of the substance in which the current is flowing. Power losses are undesirable for several reasons. Excessive power loss decreases selectivity in resonant circuits and increases noise. The relationship between power loss and energy storage in an inductor is measured by a quantity called the quality factor Q. The goal is to maximize Q, which can be done by minimizing power losses; i.e., Q is inversely proportional to the power loss.
Referring now to FIG. 3, which will help illustrate this point, a typical integrated circuit 100 comprises a semiconducting substrate 12, a dielectric 14, and a spiral inductor 16. Spiral inductor 16 lies in an upper layer of dielectric 14. Semiconducting substrate 12 is disposed below dielectric 14 and spiral inductor 16. Substrate electric field lines 18 and inductor electric field lines 20, named for the location at which they terminate, are emitted from spiral inductor 16, pass through dielectric 14 and penetrate substrate 12, causing an electric current to flow therein. Substrate electric field lines 18 represent a parasitic electric field from spiral inductor 16 which terminates in substrate 12, while inductor electric field lines 20 represent a parasitic electric field from one side of spiral inductor 16 which passes through substrate 12 and terminates on the opposite side of spiral inductor 16. Both forms of parasitic electric field (those represented by reference numerals 18 and 20) cause displacement current to flow in substrate 12. This displacement current causes a power loss in spiral inductor 16. This power loss is equal to I2R, where I represents the current flow and R represents the resistance. Semiconducting substrate 12 has an R value that is lower than an insulator would have, but R for a semiconductor is by no means zero. Spiral inductor 16 thus experiences a non-negligible, even significant, power loss.
Spiral inductor 16 is characterized by quality factor Q, which is the ratio of energy stored to power lost in the inductor. Higher Q values mean better inductor performance. In order to maximize Q, power loss must be minimized.
To minimize power loss one must prevent the electric field generated by the inductor from penetrating into the substrate. This can be accomplished by inserting a ground plane into the chip between the inductor and the substrate. Because it is grounded this plane has a much lower resistivity than does the substrate, leading to a power loss that is lower than that experienced with the substrate alone. This approach works well in applications where the ground plane can be well-separated from the substrate, as in GaAs chips where a typical separation can be around 300 microns. However, when a Si substrate is used, that relatively large separation isn""t possible and the electric field enters the substrate before the ground plane can affect it. Therefore, in order to produce the desired shielding effect in a Si chip, a ground plane must be placed very close to the inductor, perhaps 10 or 12 microns away at most.
The problem that then arises is that with the ground plane occupying a space so close to the inductor, the inductor""s magnetic field causes a current known as image current or loop current to flow in the ground plane. This image current flows in such a way as to oppose the magnetic field that is inducing it, as required by Lenz""s law. The result of this induced current flow is a drop in inductance which leads to a dramatic drop in Q. This result is just the opposite of what was intended.
A solution to the image current problem is suggested in a paper authored by C. Patrick Yue and S. Simon Wong appearing in the IEEE Journal of Solid-State Circuits, Vol. 33, No. 5, May 1998 entitled xe2x80x9cOn-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC""s.xe2x80x9d The paper proposes the use of a ground plane in which radial cuts have been made. These cuts interrupt and prevent the flow of the image current but do not cause the ground plane to lose its shielding effect with respect to the electric field. In other words, the electric field emanating from the inductor still preferentially penetrates the ground plane, where it is terminated. The result is an arrangement where the electric field is kept from penetrating the substrate, eliminating the power loss discussed above, while the induced image current in the ground plane, with its attendant problems, is simultaneously prevented. This solution is not without its drawbacks, however, and in spite of its popularity, some problems remain, as discussed below.
FIG. 4 shows a chip that uses the patterned ground plane approach. Typical integrated circuit 100 is now shown with patterned ground plane 22 inserted in a lower layer of dielectric 14 below spiral inductor 16. Patterned ground plane 22 is provided for the purpose of terminating the electric field emanating from spiral inductor 16. When substrate electric field lines 18 and inductor electric field lines 20 encounter a ground plane, the current they generate has a path of very low resistance to follow. This path leads away from semiconducting substrate 12 and since current preferentially follows a lower-resistivity path, the current flows to ground without penetrating semiconducting substrate 12. Thus, substrate electric field lines 18 are shown in this FIG. 4 as being terminated on patterned ground plane 22.
Cuts 24 in patterned ground plane 22 prevent the induction of image current by creating breaks and disruptions in the pathways where the image current would otherwise flow. Having no place to go the image current simply never is allowed to become a problem. In this way patterned ground plane 22 prevents the formation of image current at the same time that it terminates the parasitic electric field from spiral inductor 16, thus solving some, though not all, of the problems surrounding on-chip spiral inductor IC design. For an example of a problem that remains, consider that a patterned ground plane causes increased capacitance between itself and an inductor. This decreases the inductor""s self-resonant frequency, discussed below, and limits the attainable Q value for the inductor. Because maximizing Q is one of the prevailing goals in inductor-included IC design, such spiral to ground capacitance can be a real problem.
There is a particular frequency for a given inductor at which the inductor becomes self-resonant. At and above that frequency the inductor and the ground plane undergo a capacitive coupling which sets up a parallel resonance circuit and suppresses the inductor""s qualities. The system then acts just like a capacitor, i.e., as a storage device for electric, but not magnetic, energy. This self-resonant frequency is lowered with the introduction into an inductor-type IC of a ground plane, whether the ground plane be patterned or solid. What this means for an inductor in the presence of a ground plane is that its useful range is reduced. Beyond that shortcoming, the Yue-Wong approach limits the freedom with which the structure of a chip may be optimized for a particular application. Therefore, there existed a need to provide an inductor-included semiconductor device designed to reduce or substantially eliminate unwanted capacitive coupling between the inductor and ground while retaining its field-terminating effect and allowing for design optimization.
The present invention provides a way to avoid lowering an inductor""s self-resonant frequency, thus preserving the inductor""s useful operation over a wider range, while retaining the beneficial field-terminating effects of the patterned ground plane approach. The invention also allows the semiconductor to be optimized for a particular application.
According to the present invention, a semiconducting device is provided comprising a ground plane disposed between a spiral inductor and a conductive substrate. The ground plane is cut into a plurality of ground strips in order to prevent the flow of image current that would be induced in a solid ground plane by the magnetic field of the inductor. The ground strips are capacitively linked to the inductor by multiple connecting posts called conducting vias. These conducting vias are preferably formed out of a low-resistivity metal like copper or aluminum and act to terminate the parasitic electric field without excessively increasing the capacitance to ground. In the most preferred embodiment, fabrication of the conducting vias into the back-end-of-line (BEOL) metallurgy is accomplished by simply adding the via patterns to existing mask level designs and performing standard damascene fill processes as is currently practiced to form test via chains. The invention can thus be manufactured relatively inexpensively because no additional steps are necessary in the fabrication process. A further advantage of the invention is that it acts like a Faraday cage to eliminate unwanted electromagnetic radiation in the space inside the box formed by the inductor, the ground strips, and the vertical conducting vias.
Because the integrated circuit of this invention is simple to manufacture, it is easy to optimize the number and placement of the conducting vias to serve the integrated circuit""s intended purpose. The placement and density of the conducting vias would be optimized for a particular geometry of inductor for operation at a specific frequency. This optimization process would weigh the competing priorities of terminating the electric field (increasing Q by decreasing power loss in the substrate) and decreasing the parasitic capacitance present between the spiral inductor and the ground strips (increasing the self resonant frequency and thus increasing Q). A high density of conducting vias underneath the spiral inductor would provide the most effective termination of the parasitic electric field of the spiral inductor, decreasing the power loss in the substrate. This high density configuration would also have a high spiral to ground parasitic capacitance which would tend to decrease the self resonant frequency of the structure. The density of the conducting vias would then be chosen based on two possible scenarios: maximizing Q at a particular frequency, or maximizing isolation between the spiral inductor and the substrate.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.